Crate safety_net 

safety-net

An experimental library for representing circuit netlists for EDA tool development. Take a look at some examples and the documentation.

The most important API is the Netlist struct.

Simple Example

use safety_net::{Gate, Netlist};

fn and_gate() -> Gate {
    Gate::new_logical("AND".into(), vec!["A".into(), "B".into()], "Y".into())
}

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
}

Modules

iter

A collection of iterators for the netlist

Macros

assert_verilog_eq

Compare Verilog as strings up to indentation.

filter_nodes

Filter invariants of Instantiable in a netlist. Use it like you would matches!. Example: filter_nodes!(netlist, Gate::AND(_));

format_id

Functions like the format! macro, but returns an Identifier

Structs

Attribute

An attribute can add information to instances and wires in string form, like ‘dont_touch’

AttributeFilter

Filter nodes/nets in the netlist by some attribute, like “dont_touch”

Connection

Represent a driven net alongside its connection to an input port

DrivenNet

Represent a net that is being driven by a Instantiable

FanOutTable

A table that maps nets to the circuit nodes they drive

Gate

A primitive gate in a digital circuit, such as AND, OR, NOT, etc. VDD and GND are reserved to represent logic one and zero, respectively.

Identifier

An identifier of a node in a circuit

InputPort

Represent the input port of a primitive

MutBorrowReq

Facilitates mutable borrows to driver nets

Net

A net in a circuit, which is identified with a name and data type.

NetRef

Provides an idiomatic interface to the interior mutability of the netlist

Netlist

A netlist data structure

SimpleCombDepth

An simple example to analyze the logic levels of a netlist. This analysis checks for cycles, but it doesn’t check for registers.

Enums

DataType

Signals in a circuit can be binary, tri-state, or four-state.

Error

Errors for the safety-net library.

Logic

An enum to represent four-state logic

Object

A tagged union for objects in a digital circuit, which can be either an input net or an instance of a module or primitive.

Parameter

A dedicated type to parameters for instantiables

Traits

Analysis

A common trait of analyses than can be performed on a netlist. An analysis becomes stale when the netlist is modified.

Instantiable

A trait for primitives in a digital circuit, such as gates or other components.

Functions

dont_care

Create a don’t care instance

dont_touch_filter

Returns a filtering of nodes and nets that are marked as ‘dont_touch’

false

Create a Logic::False instance

high_z

Create a high-impedance instance

true

Create a Logic::True instance

Type Aliases

AttributeKey

A Verilog attribute assigned to a net or gate in the netlist: (* dont_touch *)

AttributeValue

A Verilog attribute can be assigned a string value: bitvec = (* dont_touch = true *)

GateNetlist

A type alias for a netlist of gates

GateRef

A type alias to Gate circuit nodes